Go to the table of contents for the November 6, 2000 issue of Electronic Design
Ashok Bindra
Analog, Power Devices &
DSP
System-on-a-chip (SoC) solutions have primarily been digitally intensive, comprised of a micro-controller/DSP core, memory, logic, interfaces, and other similar functions on the same die. In terms of flexibility and reconfigurability, these CPU-centric designs have been dictated by the programmability of the on-chip processor and memory. Until now, analog functions have been minimally programmable. Plus, the peripherals and I/Os surrounding the processor have been fixed for given system requirements.
But as the system needs change with evolving standards, the SoC landscape comes under constant pressure to rapidly adapt to these standards. Cost and time-to-market issues are demanding a new level of system flexibility and reconfigurability. Therefore, users are seeking a device architecture that can be quickly molded to fit system architecture and software needs at the same time as peripheral and I/O configuration can be dynamically redefined at run time.
This has motivated startup Cypress MicroSystems Inc. to exploit its parent's strengths in programmable technologies, intellectual properties (IPs), and microcontroller architectures. By combining these attributes with process capabilities, the company has spawned a new generation of high-speed programmable SoC devices, called PSoCs. Cypress MicroSystems, a creation of Cypress Semiconductor Corp., was launched in September 1999 to accelerate the development of PSoC solutions for the fast-growing communications, control, and data-acquisition markets.
In short, the PSoC shifts the processor-centric SoC toward the reconfigurability of the I/Os and peripherals on-the-fly. "It enables a designer to extract more value out of the same resources on-chip," states Nathan John, director of marketing at Cypress MicroSystems.
According to Dennis Seguine, principal applications engineer at the company, this is aided by a PC-based integrated design environment that's tightly coupled to the PSoC architecture. "Using this high-level development software, a user can quickly configure and reconfigure analog and digital arrays of the device on a PC screen. And upon satisfaction, the user can then map the system configured onto the PSoC chip by the click of an icon," Seguine remarks.
By allowing the user to work with menus and graphical icons on-screen, this Windows-based IDE permits a user to drag and drop higher-level functions in appropriate boxes and create the end system in minutes. Once the system configuration is finalized, it's stored in the flash memory on-chip. Upon power-up, the contents of the flash are transferred into register space that holds the configuration information. Also, this system configuration can be easily and quickly modified as the system requires change.
Built around a high-performance microcontroller core, a PSoC is created by adding a collection of analog and digital building blocks that allow efficient implementation of peripherals and I/Os used in a variety of embedded applications (Fig. 1). These building blocks, called SoCblocs, enable the designer to define unique functions during the configuration of the device.
In fact, these SoCblocs are further interconnected into what are called user modules. "The user module is a useful function analogous to an on-chip peripheral," John says. "Furthermore, SoCblocs can be interconnected in two fundamental ways. In parallel, they extend the precision of a function. For example, a wider timer or a higher-precision analog-to-digital converter (ADC) can be achieved. In serial, the building blocks can be configured to accomplish processing that would otherwise require multiple off-processor chips. For instance, an output of a sensor can go through a prescale amplifier, bandpass filter, and an ADC on the same PSoC chip."
The first member of the PSoC family to be implemented holds 12 analog and eight digital SoCblocs. The 12 analog SoCblocs consist of four continuous time (CT) building blocks, and eight switched-capacitor (SC) blocks (Fig. 2).
While the CT functions are optimized for building programmable-gain amplifiers (PGAs) with multiplexed inputs and outputs, differential amplifiers, and very fast comparators, the SC circuits can be interconnected to achieve functions like programmable filters, successive-approximation-register (SAR) ADCs, multislope ADCs, digital-to-analog converters (DACs), and other similar functions. Potential circuits that can be generated by the digital arrays are such functions as timers, counters, UARTs, CRC generators, pulse-width modulators (PWMs), and various other digital functions.
Using on-chip analog and digital multiplexers and switches, these SoCblocs are interconnected to achieve higher-level functions, labeled user modules by designers at Cypress. To make life easier for the user, the low-level details of the SoCblocs and their interconnection techniques are transparent to the user. The company has taken the trouble of interconnecting the underlying analog and digital SoCblocs and creating a library of analog and digital user modules.
Cypress has crafted about 40 analog user modules. Some of these are SAR ADCs, incremental ADCs, delta-sigma ADCs, and DACs. Also, there are differential comparators, programmable low/high/bandpass/bandstop filters, PGAs, sample-and-hold amplifiers, waveform generators and detectors, and modulators and demodulators. Likewise, the digital portion offers nearly 30 user modules, which include timers, counters, PWMs, serial transmitters/receivers, full UARTs, SPI master/slave interfaces, CRC generators, pseudorandom generators, and motor-control circuits.
Both the analog and digital user modules can be combined to configure the system for a specific application. To demonstrate this capability, consider a four-channel pressure data-acquisition system. In this design, differential outputs from four pressure sensors are fed into two on-chip 4-by-1 multiplexers. Then, the multiplexer outputs are fed to a high-impedance instrumentation amplifier (IA) that's made of two analog CT SoCblocs (Fig. 3). This amplifier can be configured to have the same fixed gain for all of the channels or a separate programmed gain for each channel, depending on calibration requirements. Additionally, the IA drives a two-pole, biquad low-pass filter that's constructed from two analog SC SoCblocs.
To set the filter corner frequency, the PSoC includes a digital SoCbloc configured as a timer. The filter output drives a 14-bit incremental ADC, which is built using a single analog SC SoCbloc and two digital SoCblocs. One of the digital SoCblocs functions as a sample-rate timer, while the other accumulates the lower 8 bits of the 14-bit conversion. The upper 6 bits are accumulated in the system software.
Pressure sensors often have offset voltages, which are compensated by driving an adjustable current into one of the bridge outputs. The current is adjusted by setting the duty cycle on the PWM that's configured using a single digital SoCbloc. Offset compensation values for the PWM are determined during a calibration routine. The on-chip temperature sensor is scanned directly into the ADC as an alternate input. Aside from pressure sensors, the only off-chip components used in this application are RC networks.
"The user modules define the internal setting within the SoCblocs, so that a specific function can be accomplished," John says. The company intends to expand this library as an on-going effort, adding even higher-level functions in the future. "The number of combinations are unlimited," he adds.
Employing the IDE software known as the PSoC Designer, a user can interconnect these higher-level user modules into a desired system by utilizing icons on the PC screen. "The capability to interconnect these user modules into a system is unique to this architecture," John notes. 'The user doesn't have to learn the minute details of the architecture and its interconnects. Instead, the designer can concentrate on higher-level functions and the end performance of the desired system. Both analog and digital user modules can be mixed and matched to obtain the end result."
The PSoC Designer comprises three subsystems. These include a device editor, an application editor, and a debugger. In the device editor mode, user modules are selected, pins are assigned, and register mappings are established (Fig. 4 below). The debugger provides hardware in-circuit emulation, thereby enabling the user to check breakpoints, trace memory, and observe traditional processor resources.
4. The PSoC Designer is an integral part of the Windows-based development process. Its device editor employs a graphical interface to connect user modules, which are next mapped onto the SoCblocs on-chip. Finally, the user selects the pin assignments.
The CY8C25/26xxx is the first PSoC family. It's built around the 8-bit M8C microprocessor core. It includes a multiplier/accumulator and offers six to 44 general-purpose I/Os with a variety of programmable options. Multiple oscillator choices are available too for clocking the CPU, as well as analog and digital SoC-blocs. The amount of code and data memory depends on the device type. For code space, 4 to 16 kbytes of programmable flash are offered. For data, the SRAM density goes from 128 to 256 bytes.
The first four members of the CY8C25/26xxx family are made on the company's proprietary silicon-oxide/nitride-oxide silicon (SONOS) programmable nonvolatile process, which is integrated with Cypress' high-volume CMOS-based SRAM process. The procedure requires three additional masks to the standard process to provide nonvolatile memory and the flexibility of reconfiguration at the system level. The roadmap shows future PSoCs migrating to deep-submicron CMOS by the end of 2001.
Price & Availability
The first four PSoCs, the CY8C25122, CY826233, CY8C26443, and the CY8C26643, have been implemented in 0.35-µm CMOS. They are sampling Q1 and Q2 of 2001, with volume production to begin in late Q2 of 2001. These devices will be available in 8-pin through 48-lead PDIPs, SOICs, and SSOPs. The C25122 comes in an 8-pin PDIP package only, while the C26233 is an 20-pin version in PDIP, SOIC and SSOP packages. The C26443 and C26643 are encased in 28-lead and 48-lead housings, respectively, with the 28-pin in PDIP, SOIC and SSOP packages, the 48-pin in PDIP, SSOP and 44-pin TQFP packages. In 1000-piece quantities, the price range is $1.79 each for the low pin-count CY8C25122 to $3.53 each for the highest pin-count CY8C26643. The development kit costs $125 (MSRP). The C language compiler is $145 (MSRP).
Cypress MicroSystems, 22027-17th Avenue, Suite 201, Bothell, WA 98021; (425) 939-1000; Web site: http://www.cypressmicro.com/
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